In recent years, in response to high integration of semiconductor integrated circuit chips, the number of pins in devices (semiconductor device) such as IC and LSI has been increasing. Meanwhile, demand for mounting these devices on a substrate in high density has also been increasing, fostering the advancement of a smaller package. As a result, in testing of these devices, the pin interval becomes less than the diameter of a probe used in the test, which makes it difficult to employ a so-called in-circuit method, which has been conventionally used to perform measurements by bringing a probe into contact with a pattern surface of a print substrate.
In the light of this problem, a unique measure has been taken to change positions of test pads, which, however, requires an additional substrate space, preventing high density mounting. Also, in a BGA (Ball Grid Array) package, a ball lead is disposed on a rear surface of the package and once surface mounting is secured, it becomes impossible to make a probe contact.
The above problem becomes especially notable when the number of pins is increased in response to high integration in what is called a stacked package in which a plurality of semiconductor integrated circuit chips are provided in a stacked structure of upper and lower layers or multiple layers, or a multi-chip module in which semiconductor integrated circuit chips are disposed on a plane surface.
To solve these problems, there has been development of a boundary scan testing method as a new testing method for a substrate mounting a plurality of IC packages, which is called a JTAG test or which is in accord with IEEE 1149.1. In recent years, virtually all micro processors as well as some of the peripheral circuits are made compatible with this boundary scan test. The boundary scan test is a method for testing whether pins of IC or LSI package devices mounted on a print substrate are properly connected by feeding signals from a tester such as an external host computer of the print substrate.
A device compatible with the boundary scan test has a structure, for example, as shown in FIG. 6, and it includes, in addition to a core logic 1 for realizing an intended function of the device, a boundary scan register (“BSR” hereinafter) 2, instruction register 3, bypass register 4, option register 5, test access port (“TAP” hereinafter) 6 for controlling these elements, and controller (“TAPC” hereinafter) 7 for controlling the TAP 6. The core logic 1 may have any arrangement.
The TAP 6 is a serial interface which performs input and output of commands, data, and test result with respect to the core logic 1, and in accordance with the specifications of the boundary scan test, it includes five signal lines TDI, TDO, TCK, TMS, and TRST, of which TRST is optional. The BSR 2 is made up of a serially connected shift registers 2s called “cells”, which are provided between pins 8 and input and output terminals of the core logic 1, and the shift registers 2s perform a function equivalent to that of a conventional probe and connect the signal lines TDI and TDO and the input and output terminals of the core logic 1. Between the signal lines TDI and TDO are provided the bypass register 4, instruction register 3, and option register 5, which are disposed parallel to each other.
The TDI is a signal line for serially inputting commands and data with respect to the core logic 1, and TDO is a signal line for serially outputting data from the core logic 1, and TCK is a signal line for supplying a test clock independently from a system clock which is exclusive to the core logic 1, and TMS is a signal line for controlling a test operation, and TRST is a signal line for initializing the TAPC to be asynchronous. The boundary scan test is enabled by controlling these five signal lines with an external host computer.
The boundary scan test is discussed, for example, in “Fundamentals and Applications of JTAG Test” (published by CQ Publishing Co.; published date: Dec. 1, 1998) and Japanese Unexamined Patent Publication No. 322988/1993 (Tokukaihei 5-322988) (published date: Dec. 7, 1993).
FIG. 7 is a drawing explaining a method of a conventional boundary scan test. On a print substrate 11 to be subjected to the test are mounted a plurality of devices IC1, IC2, . . . , and ICn (will be indicated by reference symbol “IC” when referring to the chips in general). On a periphery of the print substrate 11 is mounted a connector 12, which is connected to a host computer 13.
In each device IC, pins corresponding to the signal lines TCK, TMS, and TRST are connected, parallel to each other, via a pattern formed on the print substrate 11, to their corresponding pins of the connector 12. Meanwhile, with regard to pins corresponding to the signal lines TDI and TDO, a pin corresponding to the signal line TDO and a pin corresponding to the signal line TDI are successively and serially connected to each other between devices of preceding and following stages, and a pin corresponding to the signal line TDI of the device of the first stage and a pin corresponding to the signal line TDO of the device of the last stage are connected to their corresponding pins of the connector 12, respectively.
In the print substrate 11 structured as above, each device IC is controlled by the host computer 13 so as to carry out the boundary scan test all at once with respect to all the device ICs. Note that, a discrete function test of each device is individually performed one after another for each device IC using other pins.
However, in devices such as the stacked device or multi-chip module in which a plurality of semiconductor integrated circuit chips are integrally sealed, so long as the chips are integrally sealed, in order to enable the boundary scan test, each chip requires the five signal lines as noted above and the number of pins provided becomes large, and in response to this increase in the pin number, the test pattern length on the substrate is increased. Further, the test needs to be performed for the number of chips provided.